`timescale 1ns / 1ps
module CU (
    input [15:0]IR_input,
    input [7:0]FLAG_input,
    input clk,
    input rst_n,
    input step_mode,
    input step,
    input load_mode_en,
    (*MAX_FANOUT=10*)output reg[47:0]  control_signal//48bit控制信号
);
    // reg [2:0] CAR_control;
    // always @(posedge ~clk ) begin
    //     CAR_control<=control_signal[2:0];
    // end
    wire [2:0] CAR_control;
    wire [6:0] CAR_addr;
    wire [1:0] CAR_state;
    CAR CAR_inst (
        .clk(clk),
        .rst_n(rst_n),
        .CAR_control(CAR_control), 
        .IR_input(IR_input),
        .FLAG(FLAG_input),
        .index(CAR_addr), //7bit地址给CM
        .step_mode(step_mode),
        .step(step),
        .load_mode_en(load_mode_en), //下载模式使能信号
        .CAR_state(CAR_state)
    );
    wire [47:0] spo;
    assign CAR_control=spo[2:0];
    always @(posedge clk) begin
        if (CAR_state[1]) begin
            control_signal<=spo;
        end else begin
            control_signal<=0;
        end
    end
    // assign control_signal=CAR_state[1]?spo:47'b0;

    CM_rom CM(
            .a(CAR_addr),      // input wire [6 : 0] a地址
            .qspo(spo),  // output wire [47 : 0] spo输出
            .clk(clk)

    );

    
endmodule